FIG. 1 is a layout diagram of a conventional A/D conversion device as described in Japanese Laid-open Patent Application No. H. 9-269870.
This A/D conversion device comprises: a multiplexer (MPX) 1 that selects and outputs one of n-channel analogue signals than are input from n input terminals AI0 to AIn-1; an A/D converter (ADC) 2 that converts the analogue signal that is supplied from the multiplexer 1 to a digital signal and outputs this digital signal; a conversion result register 3 that holds the converted digital signal; and a plurality of control registers 4 in which are set for example operating instructions from a CPU or the like, through a bus 9. Also, this A/D conversion device comprises: a sequencer 5 that controls the multiplexer 1, A/D converter 2 and for example the conversion result register 3 in accordance with the set values of the control register 4, and decoders (DEC) 6, 7 that control changeover of the multiplexer 1 and the conversion result register 3, respectively, in accordance with instructions from this sequencer 5.
The control register 4 comprises for example a start/stop instruction register 4a for inputting start and stop instructions for A/D conversion; a conversion mode setting register 4c for setting the conversion mode to scanning mode or select mode; and a conversion channel setting register 4b for setting the initial channel or the selected channel of scanning.
In this A/D conversion device, when scanning mode is set in the conversion mode setting register 4c, for example “n-2” is set in the conversion channel setting register 4b, and, in addition, a start instruction is set in the start/stop instruction register 4a, A/D conversion in accordance with scanning mode is commenced. In this case, “n-2”, which was first of all set in the conversion channel setting register 4b, is supplied to the decoders 6, 7, causing the input signal of the input terminal AIn-2 that is selected by the multiplexer 1 to be converted to a digital signal by the A/D converter 2, and to be stored in the result register RRn-2 of the conversion result register 3. Next, the value of the conversion channel setting register 4c is decremented by 1, becoming “n-3”, and the input signal of the input terminal AIn-3 is converted to a digital signal and is stored in the result register RRn-3 of the conversion result register 3. The same processing is successively performed as far as the input signal of input terminal AI0, the conversion result of the input signal of this input terminal AI0 is stored in the result register RR0, and A/D conversion in accordance with scanning mode is thereby completed. After this, the conversion result that was stored in the result registers RR0 to RRn-2 of the conversion result register 3 is read via the bus 9 by the CPU or the like. When a complete scanning mode conversion cycle has been completed, a condition is produced in the conversion mode setting register 4c in which the continuous scanning mode can be set, in which a scanning mode conversion cycle can again be repeated: when the continuous scanning mode has been set, the scanning mode operation as described above is repeated.
On the other hand, when select mode is set in the conversion mode setting register 4c, for example “n-2” is set in the conversion channel setting register 4b, and, in addition, a start instruction is set in the start/stop instruction register 4a, A/D conversion is performed in accordance with the select mode. In this case, “n-2” that was set in the conversion channel setting register 4b is supplied to the decoders 6, 7 and the input signal of the input terminal AIn-2 selected by the multiplexer 1 is converted to a digital signal by the ADC2, and stored in the result register RRn-2 of the conversion result register 3. In this way, A/D conversion in accordance with the select mode is completed. Thereafter, the conversion result stored in the result register RRn-2 of the conversion result register 3 is read by the CPU or the like via the bus 9.
In this way, in this A/D conversion device, a scanning mode for continuous A/D conversion of a plurality of input signals in a fixed order, and a select mode for individual A/D conversion of any desired input signal with any desired timing are provided, so these two conversion modes can be separately employed as needed.
However, the A/D conversion device described above was subject to the following problems.
For example, when used in engine control of an automobile, the input signals may include the rotational speed of the engine or vehicle wheels, the running speed of the vehicle, and the temperature of the engine or external atmosphere, the sensors used to detect these being arranged in respectively different locations and being connected with the A/D conversion device through cables.
In addition, the type and number of sensors depends on the type of vehicle and the form thereof. Consequently, in the scanning mode of a conventional A/D conversion device, the sequence of connection of the cables from the sensors must be decided beforehand, in order to process these input signals, and there was therefore the problem of a lack of flexibility.
Also, in the case where it was required for example to input an input signal of a high degree of urgency twice during a single scan, it was necessary to connect a cable from a single sensor to two input terminals, giving rise to problems in terms of hardware limitations.
In the case where it is necessary to convert a specified analogue input signal a plurality of times, this can be achieved by the continuous scanning mode, but time is wasted in conversion of unrequired analogue input signals other than the specified analogue input signal. In order to avoid this, the means adopted in a conventional A/D conversion device was that the same operation was repeated by software so as to effect conversion exclusively of the analogue input signal that was selected by the select mode, and the conversion start timing had to be controlled by software: this led to the problem of incurring a considerable software processing load. This problem becomes marked when calculating the differential of a designated analogue input signal with a converted digital value.
Also, when a plurality of analogue signals were continuously converted to digital signals, although an interrupt or the like indicating completion of conversion was employed in order to perform reading of the conversion result register data through the bus connected with the CPU or the like, it was necessary to read all of the conversion result register data as far as the next conversion, and this presented the problem of imposing restrictions on software processing.